The present invention relates to voltage regulators, and in particular, to circuits and methods for regulating voltage using constant transconductance.
Low drop out (LDO) regulators are important power management building blocks. This is especially true for portable applications such as cellular phones, personal digital assistants (PDAs), and digital cameras.
Many LDO regulators employ metal oxide semiconductor (MOS) technology in order to reduce the quiescent current of the device. Power transistors such as power P-channel MOS field effect transistors (FET) are used to supply the regulated voltage by using the transistor to pass current to the load. The transconductance (gm) of the output P-channel power FET typically changes with the square root of the load current (Iload).
This square root dependence of gm on Iload may limit the stability of the voltage regulator. For example, for some LDO regulators the output stability is dependent on an output capacitor. FIG. 1A illustrates a prior art LDO regulator 100 which uses capacitor Cload 106 to stabilize the output Vout 102. FIG. 1B illustrates a graph 120 having frequency plots 121-123 depicting the loop gain associated with different loading of the prior art LDO voltage regulator 100 of FIG. 1A. The frequency at which the loop gain crosses 0 dB is known as the unity gain bandwidth (GBW), and is proportional to gm/Cload in this topology. Because gm increases with Iload. The GBW also increases with Iload.
Frequency plot 121 illustrates a condition in which load 108 of LDO regulator 100 of FIG. 1A is an open circuit (i.e. no load) condition. Frequency plot 121 illustrates a pole frequency 124 (indicated with dashed line) corresponding to an internal node of the LDO that will not change with load current. Since the pole (i.e. intersection of dashed line and frequency plot 121) is below the 0 dB axis, the LDO regulator 100 is stable for the no load condition.
Frequency plot 122 illustrates a condition in which a load current (“Iload”) of LDO regulator 100 of FIG. 1A is a load greater than the load corresponding to frequency plot 121. Frequency plot 122 illustrates the changes associated with increasing Iload, and the corresponding increase in gm, cause the zero dB frequency to increase. Since the gain bandwidth (GBW) frequency of the LDO loop is proportional to gm/Cload, the GBW frequency increases towards the pole frequency 124. However, since the pole frequency 124 is still below the 0 dB axis, the LDO regulator 100 remains stable for this load condition.
Frequency plot 123 illustrates a condition in which load 108 of LDO regulator 100 of FIG. 1A draws a load current that is greater than the load current corresponding to frequency plot 122. Frequency plot 123 illustrates how the corresponding change in gm increases such that the loop gain at pole frequency 124 is above the 0 dB axis. The LDO regulator 100 becomes unstable for this load condition.
Increasing the value of Cload to limit the GBW may stabilize LDO regulator 100. However, this may result in an oversized (or expensive) capacitor being used. This may also result in poorer transient response due to the lower bandwidth.
Prior art solutions to this problem rely on additional circuitry for generating an internal zero to cancel the pole that also varies with the load current. This zero tracks the GBW and provides additional phase to keep the loop stable over the entire load current range. One disadvantage of this technique, however, is that forcing the two frequencies to track each other over all conditions is not easy, and sometimes requires complex and expensive additional circuitry. Furthermore, if tracking is not maintained, it may result in undesirable pole-zero frequency doublets that can degrade the LDO's transient response.
FIG. 1C illustrates another prior art LDO regulator 130 which uses Miller compensation capacitor Cc 138 to stabilize the output Vout 102. This approach suffers from similar problems described in connection with the circuit of FIG. 1A. FIG. 1D illustrates a graph 140 having frequency plots 141-143 depicting the loop gain associated with different load currents of the prior art LDO voltage regulator 130 of FIG. 1C.
The Miller compensation capacitor Cc 138 “splits” the internal poles of LDO regulator 130 into a low frequency dominant pole, and a 2nd order pole that is proportional to gm/Cload where gm again is a function of the load current. Frequency plot 141 illustrates a problem in the no load or light load condition when gm may be very small or zero. The 2nd order pole 144 of frequency plot 141 now becomes very small due to the fact that the output stage (e.g., gm) is not strong enough to “split the poles”. In this case the 2nd order pole 144 can become lower than the GBW resulting in insufficient phase margin for stability.
Frequency plot 141 illustrates the no load condition of LDO regulator 130 of FIG. 1C. Frequency plot 141 illustrates how the 2nd order pole becomes lower such that pole frequency is above the 0 dB axis and LDO regulator 130 becomes unstable for this load condition.
Stabilizing the LDO regulator 130 may rely on biasing the output stage with a minimum current. This may be accomplished using the current in the LDO regulator 130 resistive divider (i.e. the current through resisters 134 and 135). This may also be accomplished using a special current buffering scheme that pushes the 2nd order pole to a higher frequency even at Iload=0. Another method may consist of adding a buffer amplifier which replaces the GM stage as the output stage. This may be a source or emitter follower. These approaches are undesirable because of the increased quiescent current to the LDO regulator 130.
Thus, there is a need for improved regulators. The present invention solves these and other problems by providing regulators with constant transconductance circuits.